In recent digital cameras, solid-state imaging devices (for example, complementary metal oxide semiconductor sensors, or CMOS sensors) have an increasing number of pixels due to reduction in pixel cell size. The mainstream of the market is high-definition solid-state imaging devices including 10 million pixels or more. In order to implement a read-out technique for these high-definition solid-state imaging devices, a typical approach is to utilize a column parallel analog-to-digital (hereinafter referred to as “A/D”) converting solid-state imaging device as described in Patent Literature 1 (PTL 1). The device includes A/D converting circuits each provided to a corresponding one of columns of pixel arrays, and performs A/D conversions, at a time in a horizontal scanning period, on pixel output signals for one row of pixel array. As this column parallel A/D converting circuit, a single-slope A/D converting circuit whose circuit size is relatively small is typically used, due to an area limitation, for each column, determined based on dot pitch. In recent years, a burst mode and a video capturing mode of digital still cameras are familiar as functions with extra values. Such functions are benefits brought by the column parallel A/D converting solid-state imaging device.
However, the column parallel A/D converting solid-state imaging device develops random jitter—that is, what is referred to as random row noise—for each row in image data, due to random jitter of a reference signal applied in a horizontal direction with respect to a pixel array. In recognizing images, human eyes sensitively recognize patterns in vertical and horizontal directions and temporal jitter. Hence, it is particularly important for the column parallel A/D converting solid-state imaging device to reduce the random row noise.